Publications – VERITAS Lab
S. Gogri, J. Ju, A. Tyagi, et alDVCON’20, San Jose, CA, March 2020 https://dvcon-proceedings.org/wp-content/uploads/machine-learning-guided-stimulus-generation-for-functional-verification.pdf
Machine Learning-Guided Stimulus Generation for Functional Verification Read More »
S Gogri, A Tyagi, M Quinn, J Hu23rd International Symposium on Quality Electronic Design (ISQED), September 2022 https://ieeexplore.ieee.org/document/9806210
R. Kande, A. Crump, G. Persyn, P. Jauernig, A. Tyagi, A. Sadeghi, J.V. Rajendran31st USENIX Security Symposium, August 2022 https://www.usenix.org/conference/usenixsecurity22/presentation/kande
P. Sengupta, A. Tyagi, Y. Chen, J. HuInternational Conference on Computer Aided Design, November 2022 https://dl.acm.org/doi/10.1145/3508352.3549375
How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning Read More »
C. Chen, R. Kande, F. Andersen, A. Tyagi, A. Sadeghi, J. Rajendran32nd USENIX Security Symposium, August 2023 https://www.usenix.org/conference/usenixsecurity23/presentation/chen-chen
HyPFuzz: Formal-Assisted Processor Fuzzing Read More »
P. Sengupta, A. Tyagi, Y. Chen, J. HuIEEE/ACM MLCAD Workshop, September 2023 https://ieeexplore.ieee.org/document/10299879
Quick Identification of Timing Critical Components in RTL Designs Read More »
P. Sengupta, A Tyagi, J Hu, VK Rajan, H Mostafa, S MajumdarACM/IEEE International Symposium on Machine Learning for CAD, September 2024 https://dl.acm.org/doi/10.1145/3670474.3685962
MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network Read More »
M Luu, S Jasper, K Le, E Pan, M Quinn, A Tyagi, J HuACM/IEEE International Symposium on Machine Learning for CAD, September 2025 https://arxiv.org/abs/2506.03590
VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration Read More »
S Jasper, M Luu, E Pan, A Tyagi, M Quinn, J Hu, DK HoungninouACM/IEEE International Symposium on Machine Learning for CAD, September https://arxiv.org/abs/2506.10501
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis Read More »
C Liu, P Parlapalli, DK Houngninou, M Quinn, A Tyagi, J HuACM/IEEE International Symposium on Machine Learning for CAD, September 2025 https://dl.acm.org/doi/abs/10.1109/ICSE-SEIP58684.2023.00037
Improving Last-Mile Coverage in Functional Verification Read More »
